Next: v Testing Up: A 30MHz FASTBUS Previous: D Data Encoding

iv Simulation

A model of one channel of the data compactor was initially written in a behavioural language and simulated on a CAD workstation. As the design progressed models of real components were substituted for portions of the behavioural language until the whole design was modelled in real components. The one channel model was tested with several sets of synthetic data and a behavioural model of the readout system. The slave interface was tested with a `Virtual Master' and simple models of the 16 channels written in behavioural language. (Limitations in the CAD system meant that it was not feasible to simulate 19 gate arrays at the gate level simultaneously.)

Next: v Testing Up: A 30MHz FASTBUS Previous: D Data Encoding