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i Introduction

Data from the 500MHz CCD Transient Digitizers[2] consists of event pulses and noise superimposed on a fixed background level or pedestal. In order to extract event data from this background, it is necessary to subtract the pedestal from the data, then save event data having a certain minimum amplitude together with fiducial information. The 8-bit event data must also be formed into 32-bit words for readout via FASTBUS[1]. This task would take an unacceptably long time in software.

A FASTBUS module is described which was designed to compact data from a module containing sixteen transient digitizer channels. Design criteria included the following:

Several methods for implementing the data compaction function were considered initially, including microprocessor, DSP (Digital Signal Processor), Field Programmable Gate Array, Mask Programmable Gate Array, and EPLD (Extended Programmable Logic Device). Of these methods, only the Mask Programmable Gate Array offered at the time the required combination of speed, price and function (number of usable gates per chip).

One custom array is used for each channel, with a further 3 arrays in the FASTBUS interface (one PCL [3] and two ADIs [4]). Each FASTBUS module supports 16 channels.

The module prototype also served for evaluation of the PCL prototypes.

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