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A 30MHz FASTBUS TRANSIENT DIGITIZER
DATA COMPACTOR USING CMOS GATE ARRAYS
A.Daviel
TRIUMF, 4004 Wesbrook Mall, Vancouver BC ~V6T 2A3,
Canada
Abstract:
A 16 channel data compactor built at TRIUMF for the BNL787 experiment is
described. The module is designed to compact data from
a 16 channel 256 bin 500MHz CCD Transient Digitizer. Each channel accepts 8-bit
digitized data from a CCD module, performs pedestal subtraction, spike and
zero-suppression, and formats the data together with channel identifiers into
32-bit words for readout by FASTBUS. Data compaction is performed on-the-fly
at a 30MHz rate, with a 600ns initial delay. Data for all channels may be
read out in one FASTBUS block transfer operation. The module incorporates a
fully-featured FASTBUS slave interface built using a CMOS gate array (the
PCL) and two bipolar gate arrays (ADIs).
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