Data Compactor Schematics

Schematics - HPGL format:

Page 1 shows the FASTBUS interface.

Page 1

Page 2 shows the FASTBUS Segment connector and power connections.

Page 2

Page 3 shows the Channel Select logic, which routes the Busy and End of Block signals and implements the in-module broadcast. The clock and strobe buffers are also shown.

Page 3

Page 4 shows the Power Monitor circuit, Busy and Module Select indicator logic.

Page 4

Page 5 shows the daughterboard connections for channels 0 - 3. Page 5

Page 6 shows the daughterboard connections for channels 4 - 7. Page 6

Page 7 shows the daughterboard connections for channels 8 - 11. Page 7

Page 8 shows the daughterboard connections for channels 12 - 15. Page 8

Page 9 shows the input connectors and data buffers for channels 0 - 3. Page 9

Page 10 shows the input connectors and data buffers for channels 4 - 7. Page 10

Page 11 shows the optional Test Data Generator. Page 11

Page 12 shows the input connectors and data buffers for channels 8 - 11. Page 12

Page 13 shows the input connectors and data buffers for channels 12 - 15. Page 13

Page pcl/1 shows the individual connections to the PCL gate array. PCL

Page adi_lo/1 shows the individual connections to the lower ADI gate array. ADI Lo

Page adi_hi/1 shows the individual connections to the upper ADI gate array. ADI Hi

Page con_trx/1 shows the FASTBUS segment signal translators. Con Trx

Page db_1 shows the daughterboard logic. db_1

The schematics are also available as 2000 x 1500 GIF files. and as compressed PostScript files.

Andrew Daviel
TRIUMF